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Senior Hardware Design Verification Engineer
Not specifiedFull-timeHardware EngineeringCloud ComputingSemiconductors
Define and execute verification strategies for high-speed PHY digital blocks, with a focus on DSP algorithms, signal processing, and digital-analog interfaces.
Responsibilities
- Verify RTL implementations against high-level architectural reference models using bit-exact and fixed-point methods.
- Assess adaptive equalization and timing recovery systems for stability, tracking, and convergence under varied channel conditions.
- Model and verify interfaces between digital DSP blocks and analog front ends using Real Number Modeling or SystemVerilog-AMS.
- Build and maintain scalable UVM simulation environments, SystemVerilog Assertions, and functional coverage for DSP blocks.
Requirements
- Bachelor’s degree in electrical engineering, computer engineering, or a related technical field.
- At least 8 years of design verification experience focused on DSP, communication systems, or arithmetic logic blocks.
- Experience with Python, Perl, or Makefile scripting for automation.
Nice to have
- Master’s degree or doctorate in electrical engineering, computer engineering, or a related technical field.
- Experience with mixed-signal verification, including Real Number Modeling or SystemVerilog-AMS.
- Knowledge of adaptive equalization architectures and timing recovery loops.
- Proficiency in Python, MATLAB, or C/C++ for testbench automation and reference modeling.
Benefits
- 15% target bonus, equity, and benefits are listed for the US compensation package.