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IP Timing Lead
Not specifiedFull-timeHardware EngineeringElectronics Manufacturing
Lead pre-silicon IP development from constraint definition through tape-out, owning netlist generation and timing convergence from synthesis to sign-off.
Responsibilities
- Own IP-level netlist generation and timing convergence from synthesis through sign-off.
- Drive synthesis, UPF power intent, scan insertion, and external IP integration.
- Develop timing constraints for standard and complex custom designs.
- Partner with RTL, CAD, and physical design teams to optimize flows and achieve timing sign-off.
- Improve timing-analysis methods and resolve timing challenges to support convergence.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering.
- At least 5 years of relevant experience, including 2 or more years writing ASIC timing constraints and achieving timing closure.
- Expertise with static timing analysis tools, such as PrimeTime, and flow generation.
- Knowledge of ASIC timing-closure flows and methodologies.
Nice to have
- Understanding of timing corners and modes, process variation, and signal integrity.
- Experience with Tcl or Perl scripting and managing timing or SDC constraints.
- Knowledge of synthesis, DFT, and backend methodologies and tools.