Empleos de Hardware Engineering

Design and develop RTL for SoC and block-level designs, contribute to verification and synthesis, and support timing and power closure and ASIC bring-up. The role offers a choice of work location between Tel Aviv and Haifa, Israel.

Join a physical design team developing CAD methodologies and tools for ASIC design flows, from RTL to GDS, for next-generation networking devices.

Lead physical design work for complex VLSI devices, contributing to backend methodology and design flows from RTL to GDS.

Verify design-for-test (DFT) designs and implementations for chip projects. Define verification scope, build verification infrastructure, and execute test and coverage plans.

Develop physical designs for networking silicon, optimizing power, performance, and area across the RTL-to-GDS flow.

Join a networking hardware team to perform static timing analysis and achieve timing signoff for chiplet and FC designs.

Develop and verify design-for-test architectures and logic across the hardware lifecycle for complex system-on-chip products.

A networking design team seeks an STA engineer to perform static timing analysis and support DFT physical design for high-speed communication chips.

Develop AI methods and tools for chip verification, automating test generation, coverage closure and debugging. Apply machine learning and LLMs to improve pre-silicon verification workflows.

Own clocking and reset logic for next-generation networking SoCs, taking synthesizable RTL from micro-architecture through verification, physical design, and tape-out.