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SoC RTL Design Engineer
Sin especificarTiempo completoHardware EngineeringSemiconductors
Own clocking and reset logic for next-generation networking SoCs, taking synthesizable RTL from micro-architecture through verification, physical design, and tape-out.
Responsabilidades
- Design synthesizable RTL for SoC clock generation, distribution, muxing, division, gating, glitchless switching, and reset synchronization
- Define and implement SoC clock and reset architecture with the micro-architecture team
- Own clock-domain crossing infrastructure and closure across the SoC
- Review specifications and provide feedback on implementation cost, timing, area, and power
- Coordinate with physical design on clock-tree implementation, constraints, partitioning, floorplanning, synthesis, congestion, and timing convergence
- Support software and firmware teams with clock programming, DVFS, and low-power flows
- Drive design quality through lint, CDC/RDC, formal, synthesis, connectivity, and structural checks
- Support SoC integration, automation, emulation, firmware, and post-silicon bring-up
Requisitos
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering
- At least 3 years of relevant RTL or logic design experience
- Hands-on experience with Verilog or SystemVerilog and a solid understanding of synthesis, timing, and physical implementation
- Experience taking a design from micro-architecture specification through verification and physical implementation
- Understanding of clocking and reset concepts, including clock gating, muxing, dividers, glitchless switching, reset synchronization, and clock-domain crossing
- Familiarity with lint, CDC/RDC, formal checks, and synthesis tools
Se valora
- Prior ownership of SoC-level clocking or reset architecture on a taped-out chip
- Experience integrating PLLs or clock generators and developing clock-tree constraints