A
DFT Engineer
Sin especificarTiempo completoHardware EngineeringSemiconductors
Develop and verify design-for-test architectures and logic across the hardware lifecycle for complex system-on-chip products.
Responsabilidades
- Define and implement DFT architectures for complex SoCs.
- Develop and integrate MBIST, JTAG/TAP, and boundary-scan logic.
- Code and debug DFT controllers and infrastructure in Verilog or SystemVerilog.
- Run gate-level simulations to validate DFT functionality and test patterns.
- Develop and verify DFT logic using UVM testbenches, functional simulation, and coverage-driven methods.
- Participate in design reviews, DFT sign-off, and tapeout preparation.
- Collaborate with design, verification, physical design, and production/test teams.
Requisitos
- Hands-on RTL design experience with Verilog or SystemVerilog.
- Experience with chip design flows and gate-level simulation.
Se valora
- Experience with MBIST, JTAG/IEEE 1149.1, memory repair, and tools such as Synopsys DFT Compiler or Tessent.
- UVM-based verification, coverage-driven testing, FPGA or emulator environments, and scripting with Perl, Tcl, or Python.
- End-to-end chip development experience, from RTL through physical design and post-silicon validation.
Beneficios
- Continuous learning opportunities.