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Senior SoC Design Engineer
Sin especificarTiempo completoHardware EngineeringCloud ComputingConsumer Electronics
Design and develop RTL for SoC and block-level designs, contribute to verification and synthesis, and support timing and power closure and ASIC bring-up. The role offers a choice of work location between Tel Aviv and Haifa, Israel.
Responsabilidades
- Define SoC and block-level design documents, including interface protocols, block diagrams, transaction flows, and pipelines.
- Develop and debug RTL using Verilog or SystemVerilog; debug functional and performance simulations and run lint, formal verification, and power-format checks.
- Participate in synthesis, timing and power closure, and ASIC silicon bring-up.
- Contribute to test planning and coverage analysis for block- and SoC-level verification.
- Work with multidisciplinary teams across multiple sites.
Requisitos
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- At least 8 years of experience with digital design principles, RTL concepts, and Verilog or SystemVerilog.
- Experience optimizing RTL through synthesis techniques for performance and power.
- Experience with design and debugging in collaboration with design verification.
Se valora
- Experience with Python or Perl scripting.
- Experience with design sign-off and quality tools, such as lint and clock domain crossing checks.
- Knowledge of SoC architecture and assertion-based formal verification.
- Knowledge of PCIe, UCIe, DDR, AXI, or ARM processors.