Empleos de Hardware Engineering

Join a multidisciplinary R&D team developing optical fiber sensing systems for monitoring critical infrastructure. The role combines electro-optical system design, laboratory and field testing, hardware integration, and work to scale sensing equipment for production. The office is in Tel Aviv, with

Join a team working on high-speed analog interfaces for automotive SoCs, contributing to pre-silicon signal and power integrity simulations and post-silicon electrical validation and debug.

Join a Design-for-Test team developing DFT architecture, verification, and post-silicon validation for advanced semiconductor chips. Own ATPG activities from planning through pattern generation, verification, silicon bring-up, and diagnosis, and develop automation flows to reduce production test 시간을

Lead the architecture of high-performance machine-learning compute IP for cloud AI silicon, from concept and modeling through implementation, silicon bring-up, and production.

Develop and improve synthesis flows, tools, and methodologies for high-speed communication silicon, with a focus on power, performance, and area objectives.

Join a hardware team designing physical layouts for advanced IC packages used in machine-learning and data-center ASICs. Take package layouts from floor planning through tape-out and manufacturing release, working with senior engineers and cross-functional teams.

Join a networking silicon team developing high-speed communication devices. Work across chip physical design, from RTL to GDS, with a focus on power, performance, and area.

Develop and maintain front-end CAD flows and methodologies for SoC designs, helping improve RTL quality, verification, and engineering efficiency.

Design, develop, and validate embedded hardware and firmware for home-based sleep diagnostics devices. Work on-site in Raanana with software, clinical, and product teams.

Work with customer design teams to integrate and use static timing analysis and engineering change order tools, resolve timing challenges, and improve chip design flows.