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Join a networking hardware team to perform static timing analysis and achieve timing signoff for chiplet and FC designs.

Join a solution engineering team working on networking products, datacenter platforms, containers, and enterprise system software. The role combines customer problem-solving with software development.

Define architecture for host management software and firmware across networking platforms. Lead cross-functional teams and turn platform needs into scalable, reliable production solutions.

A networking design team seeks an STA engineer to perform static timing analysis and support DFT physical design for high-speed communication chips.

Develop AI methods and tools for chip verification, automating test generation, coverage closure and debugging. Apply machine learning and LLMs to improve pre-silicon verification workflows.

Own clocking and reset logic for next-generation networking SoCs, taking synthesizable RTL from micro-architecture through verification, physical design, and tape-out.

Own SOC clocking and reset logic for next-generation networking chips, taking synthesizable RTL from micro-architecture specification through physical implementation and tape-out in collaboration with cross-functional engineering teams.

Join a networking silicon team to optimize power across physical design and contribute to chip development from RTL to GDS.

Define software and system architecture for next-generation DPU management and networking platforms supporting large-scale AI and cloud datacenters. Partner across hardware, software, firmware, validation, product, and customer teams from early design through production readiness.

Lead performance strategy and optimization for large-scale AI GPU clusters and data center solutions. The role spans distributed training and inference, high-performance networking, DPU and storage use cases, and cluster observability.