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Junior Physical Design Engineer (STA)
Not specifiedFull-timeHardware EngineeringSemiconductor
Join a networking hardware team to perform static timing analysis and achieve timing signoff for chiplet and FC designs.
Responsibilities
- Run advanced static timing analysis at chiplet and FC levels using PrimeTime.
- Review and debug timing paths; understand constraints; generate SDC and timing ECOs.
- Identify convergence risks and coordinate with physical design, RTL, and DFT teams throughout project stages.
- Own timing closure and quality approval from pre-layout STA modeling through signoff.
Requirements
- Bachelor’s degree in Electrical Engineering or Computer Engineering.
- At least 2 years of experience as an STA engineer.
- Strong adaptability and ability to learn new technical areas.
- Effective communication and teamwork skills.
- Ability to develop and implement solutions.
Nice to have
- Knowledge of physical build flows and methodologies, including place-and-route, STA, and physical verification.
- Familiarity with PrimeTime.