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STA Engineer
Not specifiedFull-timeHardware EngineeringSemiconductor Manufacturing
A networking design team seeks an STA engineer to perform static timing analysis and support DFT physical design for high-speed communication chips.
Responsibilities
- Run DFT static timing analysis from RTL-driven constraints and definitions through constraint quality assurance and STA sign-off
- Handle timing constraints, environment and model generation, and timing ECOs at block and full-chip levels
- Contribute to flow development
- Work with pre- and post-silicon design experts on DFT solutions
Requirements
- Bachelor’s degree in electrical engineering or computer engineering
- 2–3 years of experience as an STA engineer
- Ability to adapt quickly to new technology and learn unfamiliar areas
Nice to have
- Knowledge of physical design flows and methodologies, including PNR, STA, and physical verification
- Knowledge of DFT flows such as ATPG, MBIST, and IJTAG
- Experience with DFT timing closure
- Knowledge of CDC
- Familiarity with physical design EDA tools such as Synopsys or Cadence