Q
Senior Physical Design Engineer
·Israel
On-siteFull-timeHardware EngineeringSemiconductor Manufacturing
Own full-chip physical design strategy, including floorplanning, power delivery, clock architecture, place-and-route, and timing closure on TSMC N5/N4P/N3. Define backend methodology, develop flow automation using Python/TCL, champion Agentic AI adoption, and lead cross-functional reviews.
Responsibilities
- Architect and own full-chip physical design strategy: floorplanning, PDN, clock architecture, PnR, and timing closure
- Define and drive backend methodology standards for advanced node tapeouts
- Lead critical timing closure efforts including MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
- Oversee signal integrity, power integrity, EM/IR, and reliability analysis
- Architect scalable PD flow infrastructure using Python and TCL
- Champion adoption of Agentic AI in design flow: define use cases, evaluate tools, prototype autonomous agents
- Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
- Interface with TSMC, EDA vendors, and internal research teams
- Mentor and technically guide junior and mid-level PD engineers
Requirements
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design experience (or Master's +5, PhD +4)
- 10+ years of experience in digital Physical Design with tapeouts on FinFET nodes (N7 and below)
- Deep expertise in full-chip and block-level floorplanning, clock architecture, STA, PnR, and physical sign-off
- Expert proficiency in EDA tools: Synopsys ICC2/Fusion, Cadence Innovus, Calibre, PrimeTime, RedHawk/Voltus, StarRC/Quantus
- Advanced Python and TCL scripting for large-scale PD automation frameworks
- Proven experience in flow development: end-to-end backend design flows
- Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges
- Strong communication skills for presenting to senior management
- Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)
Nice to have
- Experience with chiplets, 2.5D/3D IC physical design, or advanced packaging technologies
- Familiarity with AI/ML-driven EDA tool evaluation and vendor collaboration
- Prior experience in a tech lead or staff engineering leadership role