Senior Physical Design Engineer
Design networking silicon blocks from RTL to GDS, optimizing power, area, performance, timing, congestion, and physical verification for high-speed communication devices.
Responsibilities
- Perform block-level physical design under power, area, and performance constraints
- Resolve complex timing and congestion issues
- Execute RTL-to-GDS development activities, including synthesis, power and clock distribution, place and route, timing closure, power analysis, and noise analysis
- Conduct physical verification
- Contribute to physical design flow development
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or equivalent experience
- At least 5 years of relevant physical design experience
- Knowledge of physical design flows and methodologies, including PNR, STA, and physical verification
- Deep understanding of physical construction and integration
- Knowledge of LVS and DRC verification methodologies
- Experience with physical design EDA tools such as Synopsys or Cadence
- Collaborative engineering approach
Nice to have
- Familiarity with Synopsys or Cadence EDA tools
- Equivalent practical experience in place-and-route and physical design