Senior CPU Physical Design Engineer
Join a team designing future-generation high-performance microprocessors. Responsible for physical design flow from RTL to GDS: synthesis, floorplanning, place & route, timing closure, sign-off. Requires B.Sc. in Electrical/Computer Engineering and 10+ years of experience with Cadence/Synopsys EDA tools. Hybrid role based in Haifa, Israel.
Responsibilities
- Design and deliver high-performance CPU blocks from RTL to GDS.
- Execute full physical design flow: synthesis, floorplanning, place and route, CTS, timing closure, power/clock distribution, reliability, power, and noise analysis.
- Lead verification and sign-off (STA, equivalence, power integrity, LVS/DRC/ERC, structural checks).
- Optimize designs for power, performance, and area using industry-standard EDA tools.
- Contribute to methodology and automation improvements.
- Mentor junior engineers.
Requirements
- B.Sc. or M.Sc. in Electrical or Computer Engineering, or equivalent.
- At least 10 years of experience in physical design using Cadence/Synopsys implementation tools.