Hardware Performance Modeling Architect
Join a team building network simulators for next-generation networking chips. Develop cycle-accurate simulation components, analyze switch ASIC performance, and explore architectural optimizations for AI and HPC systems.
Responsibilities
- Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options for next-generation switches.
- Learn and understand the switch ASIC across all performance related aspects.
- Focus on switch hardware modeling.
- Analyze and model the communication patterns of key DL, GAI inference and training applications.
- Explore innovative ideas to improve and optimize chip systems performance.
Requirements
- BSc/MSc in Electrical Engineering, Computer Science or related field.
- Experience in developing simulation models.
- 2+ years of experience in C++ and Python.
- Strong debug skills.
- Excellent verbal and written communication skills.
Nice to have
- Master's degree in Electrical Engineering, Computer Science or related technical field.
- 5+ years of relevant practical experience.
- Experience with network simulation tools (omnet, ns3, sst, gem5).
- Demonstrated ability to innovate and lead new technologies leading to product impact.
- Experience with NVLink/Ethernet/IB technologies.