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Senior Networking ASIC Micro-Architect

Google·Israel·en
PresencialTiempo completoCommunications EngineeringCloud ComputingConsumer Internet

Lead the architecture and implementation of networking ASIC subsystems and SoCs for high-performance infrastructure hardware. The role is based in Israel, with preferred working locations in Tel Aviv or Haifa, and may require in-person interviews.

Responsabilidades

  • Lead design activities across IP blocks, subsystems, and SoCs.
  • Define block-level design documentation, including interface protocols, block diagrams, transaction flows, and pipelines.
  • Develop and debug RTL using Verilog, SystemVerilog, or VHDL.
  • Debug functional and performance simulations and perform Lint, CDC, formal verification, and UPF checks.
  • Participate in synthesis, timing and power analysis, FPGA or silicon bring-up, test-plan development, and coverage analysis for block- and SoC-level verification.
  • Collaborate with multidisciplinary and distributed engineering teams.

Requisitos

  • Bachelor’s degree in electrical engineering, computer engineering, computer science, a related technical field, or equivalent practical experience.
  • At least 8 years of experience architecting networking ASICs from specification through production, or equivalent experience.
  • At least 4 years of technical leadership experience.
  • Experience developing RTL for ASIC subsystems.
  • Experience with microarchitecture, RTL design, verification, logic synthesis, timing closure, design quality checks, physical-design considerations in RTL coding, and power analysis.

Se valora

  • Experience architecting networking switches, endpoints, or hardware offloads.
  • Experience with RDMA, packet processing, and low-latency, high-throughput, secure, reliable system design.
  • Experience optimizing hardware/software interfaces with software teams.
  • Proficiency in C++, Python, Go, or another procedural programming language.
  • Knowledge of TCP, IP, Ethernet, PCIe, and DRAM.
  • Familiarity with Network-on-Chip principles and AXI, ACE, or CHI protocols.

Compatibilidad

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