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Work on physical design and methodology for next-generation processor chips in advanced CMOS processes. Collaborate with local and global engineering teams to integrate designs and achieve design closure.

Hands-on internship for an advanced bachelor's student supporting AI research through semiconductor data collection, cleaning, transformation, and pipeline development.

Responsible for leading the design of digital blocks from architecture to implementation, driving area and timing optimization, lint, CDC/RDC analysis, and collaborating on block-level verification. Requires a B.Sc/M.Sc in Electrical Engineering and 5+ years of digital design experience with proficiency in Verilog/SystemVerilog.