Physical Design Engineer
Work on physical design and methodology for next-generation processor chips in advanced CMOS processes. Collaborate with local and global engineering teams to integrate designs and achieve design closure.
Responsibilities
- Coordinate with digital, RTL, analog, and other design teams to achieve timely convergence and integration.
- Implement and support multi-voltage designs, including place and route, static timing, and physical verification using standard EDA tools.
- Integrate AI-based design flows and drive design closure with partner teams.
- Write Shell, Python, and Tcl scripts to improve productivity through automation and AI.
- Provide technical direction, coaching, and mentoring when needed.
Requirements
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field.
- At least 4 years of progressive experience in backend physical design and verification.
- Good understanding of RTL-to-GDS flows and methodology.
- Expertise in full-chip and sub-hierarchy integration.
- Experience integrating and taping out large designs in a digital design environment.
- Scripting skills in Perl, Tcl, and Python.
Nice to have
- Experience with multi-voltage and low-power design techniques.
- Experience with Cadence Genus and Innovus.
Benefits
- Eligible for bonus plans and equity, including a new-hire grant and annual equity refreshers.
- Competitive compensation and benefits.