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Senior Power Optimization and Analysis Engineer
Not specifiedFull-timeHardware EngineeringElectronics Manufacturing
Join a switch architecture team focused on analyzing and reducing chip and unit-level power consumption. Work with architecture, ASIC design, physical design, performance, and software teams to improve energy efficiency in next-generation switch products.
Responsibilities
- Analyze full-chip and unit-level power data.
- Develop techniques to model, analyze, and reduce power consumption.
- Use pre-silicon gate-level and RTL power analysis tools.
- Develop best practices for pre-silicon power analysis.
- Perform comparative power analysis to identify trends and anomalies.
- Interpret power data with architects and RTL designers and drive resolution of power issues.
- Select and run workloads for power analysis.
- Prototype architectural features in Verilog and evaluate their power impact.
Requirements
- Bachelor’s or master’s degree in Computer Engineering or Electrical Engineering.
- At least 5 years of chip design experience.
- Experience with Verilog and ASIC design or verification.
- Strong coding and automation skills, preferably in Python, Perl, and C++.
- Ability to collaborate effectively with design teams.
- Data-driven approach to product improvement and analytics.
Nice to have
- Experience with Power Artist, PTPX, PrimePower RTL, or RTL Architect.
- Strong understanding of energy consumption, power estimation, data movement, and low-power design.