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Senior Physical Design Engineer, SoC Static Timing Analysis
Not specifiedFull-timeHardware EngineeringSemiconductorsCloud ComputingInternet Services
Lead static timing analysis and sign-off convergence for high-performance SoC designs, defining constraints, methodologies, infrastructure, and physical design trade-offs for advanced AI hardware.
Responsibilities
- Drive timing sign-off convergence for high-performance designs.
- Define timing constraints, STA methodology, infrastructure, and sign-off convergence flows.
- Collaborate with block owners to achieve project timing convergence.
- Work with logic designers on architectural feasibility studies, timing development, and RTL/design trade-offs for physical design closure.
Requirements
- Bachelor’s degree in Electrical Engineering, a related technical field, or equivalent practical experience.
- 8 years of physical design experience, including 5 years with static timing analysis.
- Experience with sign-off corner definitions, process margining, interface timing constraints, timing convergence, and frequency goal setting.
- Experience developing constraints for subsystems or complete SoC architectures.
Nice to have
- Proficiency with Tcl, Python, or Perl scripting.
- Deep familiarity with ASIC physical design flows, including synthesis, place and route, formal verification, and clock domain crossing.
- Knowledge of semiconductor device physics and transistor characteristics.