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Senior Physical Design Engineer
ClosedNot specifiedFull-timeHardware EngineeringSemiconductor Manufacturing
A semiconductor engineering team is seeking a Senior Physical Design Engineer to develop full-chip layouts for advanced networking silicon, from floorplanning through tape-out.
Responsibilities
- Perform full-chip physical layout, integration, pinning, and bump routing.
- Collaborate with block owners and project managers to drive layout convergence and quality.
- Own chip layout activities from floorplanning through tape-out.
- Support physical verification and advanced-node design implementation.
- Contribute to physical design methodology and place-and-route flow ownership.
Requirements
- Electronics Engineer certificate or bachelor’s degree in Electrical Engineering.
- At least 5 years of hands-on full-chip layout and physical verification experience.
- Strong knowledge of DRC, LVS, antenna checks, ERC, and DFM for advanced process nodes.
- Experience with Tcl, Unix, shell scripting, and Linux environments.
- Familiarity with Synopsys ICC2 or Fusion Compiler and Cadence Innovus.
- Familiarity with Synopsys ICV and Siemens Calibre physical verification tools.
- Strong attention to detail, self-motivation, and interpersonal skills.
Nice to have
- Experience defining physical design methodologies or owning full-chip/place-and-route flows.
- Orientation toward AI tools or willingness to learn them.
- Ability to work autonomously, learn independently, and contribute as a strong teammate.
Relevance
This vacancy is no longer accepting applications.