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Physical Design Signoff Engineer
On-siteFull-timeHardware EngineeringElectronics Manufacturing
Join a networking silicon engineering team developing physical design, signoff, and verification methodologies for high-speed communication chips and SoCs.
Responsibilities
- Develop physical design, static timing analysis, logic equivalence, and power integrity flows for networking chips and SoCs
- Work with block owners and full-chip timing engineers to achieve quality and timely convergence
- Develop flow and tool methodologies for timing analysis and closure
- Perform power and noise analysis, including IR-drop and electromigration analysis
- Support backend verification across multiple projects
- Solve complex physical design problems and improve implementation methodologies
Requirements
- Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or equivalent experience
- At least 2 years of relevant full-time experience
- Strong knowledge of physical design, backend CAD, static timing analysis, and timing closure
- Familiarity with PrimeTime and PrimePower
- Strong written, verbal, and presentation skills
- Ability to work independently and collaboratively with global teams
Nice to have
- Experience with signoff analysis using PrimeTime, PrimePower, RedHawk, or Formality
- Knowledge of Tcl, Perl, or Python
- Experience with power integrity, formal equivalence, or power estimation