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Physical Design Engineer
Not specifiedFull-timeHardware EngineeringElectronics Manufacturing
Work on RTL-to-GDS implementation and signoff for next-generation embedded memory test chips across advanced CMOS process technologies.
Responsibilities
- Execute place-and-route tasks from RTL to GDSII.
- Perform design signoff, including static timing analysis, EMIR, DRC, and LVS.
- Work across advanced CMOS process nodes down to 2nm and beyond.
- Automate physical design and verification flows.
- Collaborate with circuit design and integration teams.
Requirements
- At least 2 years of physical design experience from RTL to GDS.
- Hands-on experience with Cadence Genus and Innovus.
- Strong understanding of signoff processes including STA, DRC, and LVS.
- High proficiency in scripting, automation, and Linux environments, including Tcl, Python, or Bash.
- Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering.
- Ability to work independently and deliver results.