Performance Modeling Architect
Lead performance modeling and architectural exploration for next-generation networking chips supporting AI and high-performance computing. Collaborate across hardware, software, architecture, and research teams.
Responsibilities
- Develop C++ simulation models to define and evaluate networking architecture options.
- Analyze and model communication patterns for deep learning, generative AI, inference, and training applications.
- Identify performance bottlenecks and assess architectural trade-offs.
- Explore improvements to chip-system performance.
- Collaborate with architecture, research, hardware, and software teams.
- Lead technical workgroups toward solutions for future networking products.
Requirements
- Bachelor’s or master’s degree in Computer Science or Electrical Engineering.
- At least 3 years of hands-on experience.
- Proficiency in C++ and Python.
- Strong debugging skills.
- Excellent verbal and written communication skills.
- Demonstrated ownership and ability to drive technical solutions and initiatives.
Nice to have
- Master’s degree in Electrical Engineering, Computer Science, or a related technical field.
- Experience with NVLink, Ethernet, or InfiniBand technologies.
- Evidence of innovation and technical leadership resulting in product impact.