Junior Physical Design Engineer
Join a professional semiconductor engineering team developing high-speed networking chips. The role covers end-to-end physical design from RTL to GDS under demanding power, area, and performance constraints.
Responsibilities
- Perform physical design of chip blocks according to technical specifications and challenging power, area, and performance targets.
- Work on high-cell-count and high-speed design blocks.
- Resolve complex timing and congestion issues.
- Support the full RTL-to-GDS development flow, including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
- Contribute to physical design flow development.
- Support integration and static timing analysis activities.
Requirements
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or equivalent experience.
- Proven experience with RTL-to-GDS flows and methodologies.
- Knowledge of physical design flows, including place and route, static timing analysis, and physical verification.
- Strong understanding of physical construction and integration.
- Knowledge of LVS and DRC verification methodologies.
- Familiarity with physical design EDA tools such as Synopsys or Cadence.
- Collaborative and effective team player.