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CPU Design Verification Engineer
On-siteFull-timeHardware EngineeringEnterprise SoftwareData Infrastructure
An R&D hardware team is seeking a CPU design verification engineer to verify digital design blocks and processor IP through planning, constrained-random testing, formal methods, debugging, and coverage closure. The role is based in Tel Aviv or Haifa, Israel, with in-person interviews generally part:
Responsibilities
- Plan verification for digital design blocks by analyzing specifications and identifying important scenarios with design engineers.
- Create and improve constrained-random verification environments using SystemVerilog and UVM, or formally verify designs using SystemVerilog assertions and formal tools.
- Define and implement coverage measures for corner cases.
- Debug tests and collaborate with design engineers to deliver functionally correct design blocks.
- Track and close coverage gaps and support verification progress toward tape-out.
Requirements
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- At least 4 years of experience creating and using verification components and environments with a standard verification methodology.
- Experience verifying RTL digital logic for FPGA or ASIC designs using SystemVerilog or Specman/E.
Nice to have
- Master’s degree or PhD in Electrical Engineering or a related field.
- Experience with ASIC standard interfaces and memory-system architecture.
- Knowledge of CPU architectures such as ARM, x86, or RISC-V, including pipelines, caches, memory subsystems, instruction sets, and exceptions.
- Experience with performance verification of ASICs or ASIC components.
- Experience with verification techniques and the full verification life cycle.