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ASIC Design Lead, Networking IP
On-siteFull-timeHardware EngineeringData Infrastructure
Lead a networking IP design team developing custom ASIC and SoC solutions. Own IP definition, implementation, integration, and deployment from architecture through production for high-performance, low-latency systems.
Responsibilities
- Own the networking IP design team, including IP definition, implementation, and deployment.
- Establish IP development methodologies and reusable blocks across the design team.
- Define block-level design documentation, including interface protocols, block diagrams, transaction flows, and pipelines.
- Contribute technically throughout the IP development cycle and integrate IP into SoC designs.
- Develop and debug RTL using Verilog, SystemVerilog, and VHDL.
- Debug functional and performance simulations and perform Lint, CDC, formal verification, and UPF checks.
- Collaborate with architecture, software, verification, power, timing, and synthesis teams.
- Evaluate micro-architecture and logic solutions for performance, power, and area.
Requirements
- Bachelor’s degree in electrical engineering or equivalent practical experience.
- 10 years of experience designing from micro-architecture through implementation using Verilog/SystemVerilog or VHDL.
- 8 years of experience managing teams and groups.
- Experience with networking design, such as RDMA or packet processing.
- Knowledge of low-latency, high-throughput, secure, and reliable system design principles.
- Experience with chip design flow, chip architecture, design methodologies, physical design, and verification processes.
Nice to have
- Master’s degree or PhD in engineering, or equivalent practical experience.
- Experience leading chip development projects and execution.
- Ability to motivate collaborative teams and focus them on testing goals.