Senior Software Engineer, Design Verification Tools
Develop software tools and services that support design verification across chip families. Collaborate with verification engineers and EDA vendors to improve workflows and support project milestones.
Responsabilidades
- Develop and maintain an LLM harness for agentic design verification workflows; benchmark and improve workflow accuracy.
- Build and manage cloud-native services on Kubernetes, including CI/CD, containerization, alerting, databases, GUI, and monitoring.
- Gather user requirements through collaboration with design verification stakeholders.
- Write and maintain Python scripts for design simulation flows.
- Support multiple projects simultaneously.
Requisitos
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or computer science.
- Multiple years of experience in design verification or design verification CAD.
- Strong software engineering fundamentals, including data structures and algorithms.
- Track record of automating tasks and improving workflows.
- General understanding of chip design, hardware description languages, front-end design, simulation, synthesis, and physical design.
- Strong communication skills.
Se valora
- Experience with Docker, Kubernetes, HTTP servers, authentication, and authorization.
- Familiarity with LLM harnesses and frameworks.
- Python experience with asynchronous programming, Pydantic, SQLAlchemy, and FastAPI.
- SQL and database experience, including MySQL.