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Define architecture for next-generation network interface controller (NIC) and data processing unit (DPU) products. Work across software, ASIC design, verification, physical design, platform, GPU, CPU, board, and package teams to improve system performance and resolve complex full-chip issues.

Develop physical design and signoff methodologies for networking chips and SoCs, working with block owners and full-chip STA engineers to support quality and timely convergence.

Join a networking software team supporting development systems and integrations. Build tools and automation that improve CI/CD workflows, release pipelines, and development environments.

Design and implement system-on-chip clocking for complex networking chips, collaborating with physical design, CAD, package design, software, DFT, and unit-level teams.

Develop upstream Kubernetes and cloud-native capabilities that support AI workloads. Work across distributed systems, infrastructure software, API design, and open-source communities.

Lead end-to-end architecture and definition of hardware systems, adapters, and interconnects for AI cluster deployments. Work across hardware, chip design, software, engineering, and operations teams to take new technologies from concept through execution.

Join a silicon engineering team developing high-speed communication devices. Design and verify chip blocks, with a focus on performance and integration across GPUs, CPUs, and network interface cards.

Join an interconnect validation team responsible for integrating software tests for networking products into production lines. Work across engineering teams to plan, execute, automate, and troubleshoot hardware and software validation.

Lead end-to-end investigations of product failures, combining laboratory debugging, system-level analysis, and evidence from multiple engineering disciplines to establish root causes.

Join a chip design methodologies team developing shared verification solutions and improving the efficiency and quality of verification work.