SOC Clock Distribution Engineer
Design and implement system-on-chip clocking for complex networking chips, collaborating with physical design, CAD, package design, software, DFT, and unit-level teams.
Обязанности
- Design and implement SOC-level clock requirements
- Support chip-level design activities including partitioning, clock-domain crossing, trial synthesis, and design-quality checks
- Address functional and structural challenges, including functional debugging, physical-design readiness, and design-quality issues
Требования
- Bachelor’s degree in Electrical Engineering or Computer Engineering
- At least 3 years of chip-design experience
- Hands-on physical-design experience with clock distribution in products with tight power, timing, and layout constraints
- Proficiency in at least one scripting language such as Perl, Python, Bash, or Tcl
Будет плюсом
- Experience delivering designs back to RTL, physical design, and other partner teams
- Strong commitment to quality
Условия и преимущества
- Competitive salary
- Comprehensive benefits package