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Senior Full-Chip Layout Engineer
On-siteFull-timeElectrical DesignElectronics Manufacturing
Join a networking silicon engineering team responsible for full-chip physical layout and verification from floorplanning through tape-out.
Responsibilities
- Perform full-chip physical layout, integration, pinning, and bump routing.
- Coordinate with block owners and project managers to achieve layout convergence and quality.
- Own chip layout activities from floorplanning through tape-out.
Requirements
- Electronics Engineer certificate or bachelor’s degree in Electrical Engineering.
- At least 5 years of hands-on full-chip layout and physical verification experience.
- Strong knowledge of DRC, LVS, ANT, ERC, and DFM methodologies for advanced process nodes.
- Experience with Tcl, Unix, Shell, and Linux environments.
- Familiarity with Synopsys ICC2 or Fusion Compiler and Cadence Innovus.
- Familiarity with Synopsys ICV and Siemens Calibre physical verification tools.
- Strong attention to detail and interpersonal skills.
Nice to have
- Experience defining methodologies or owning full-chip and place-and-route flows.
- Orientation toward AI tools or willingness to learn.
- Ability to work autonomously with strong ownership and teamwork.