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Senior Formal Verification Engineer
On-siteFull-timeQA & Test AutomationSemiconductor Manufacturing
Join an Israeli semiconductor R&D center and lead formal verification for complex connectivity chips supporting large-scale AI infrastructure. Own verification strategy, develop reusable environments, and drive designs through sign-off.
Responsibilities
- Own formal verification environments from initial development through sign-off.
- Define and apply formal verification strategies for complex chip designs.
- Partner with architecture, design, and design verification teams to identify verification needs and requirements.
- Develop formal environments, analyze RTL designs, and use advanced techniques to uncover corner-case bugs.
- Analyze verification results, investigate failures, and work with designers on resolution.
- Architect reusable formal functions and properties for use across multiple projects.
Requirements
- Bachelor’s degree in Electrical Engineering or a related technical field.
- At least 4 years of hands-on formal verification experience in the semiconductor industry.
- Deep knowledge of formal verification methodologies, tools, and flows.
- Strong understanding of RTL design and verification principles.
- Experience with industry-standard tools such as Jasper or VC Formal.
- Strong communication, analytical, and problem-solving skills.
Nice to have
- Experience taking complex blocks or subsystems through the full formal verification lifecycle.
- Experience with SystemVerilog and UVM-based design verification.
- Knowledge of Ethernet, NVLink, UALink, or PCIe networking standards.
- Background in high-speed serial interface verification.