A
Staff Physical Design Engineer - SoC EMIR Engineer
·Israel
On-siteFull-timeHardware EngineeringSemiconductor Manufacturing
Seeking a Staff Physical Design Engineer to perform SoC EMIR analysis, ensure power integrity, and collaborate on chip-package co-analysis for high-performance AI connectivity chips in advanced FinFET nodes. Requires 7+ years of experience with tools like Ansys RedHawk or Cadence Voltus.
Responsibilities
- Perform IR drop analysis and signal/power electromigration (EM) on complex SoCs.
- Collaborate with Physical Design team to ensure full power integrity.
- Partner with Package Design engineers for Chip-Package co-analysis (CPM).
- Conduct root-cause analysis for voltage drop violations and EM risks.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or a related technical field.
- 7+ years of hands-on experience in EMIR/Power Integrity analysis for high-performance SoCs or high-speed connectivity products.
- Strong proficiency in industry-standard EMIR tools (Ansys RedHawk/RedHawk-SC, or Cadence Voltus).
- Deep understanding of EM/IR challenges in advanced FinFET nodes (7nm, 5nm, 3nm).
- Deep understanding of Place & Route flows, power grid synthesis, extraction (RC), and standard cell architecture.
- Deep understanding of EM and trade-offs between signal EM and power grid (PG) EM.
Nice to have
- Familiarity with thermal analysis tools and their interaction with electrical performance.
- Experience working with sign-off criteria and margins for high-volume production chips.
- Good understanding of timing and physical design.
- Basic understanding of packaging, top metal layers, MIM capacitor usage, and power distribution.
- Ability to write TCL scripts for STA and Fusion Compiler (FC).