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Senior Static Timing Analysis Engineer
Not specifiedFull-timeHardware EngineeringSemiconductor Manufacturing
Perform static timing analysis for high-speed I/O at chiplet and full-chip levels, supporting networking silicon from pre-layout modeling through signoff.
Responsibilities
- Run advanced static timing analysis and review and debug timing paths.
- Understand timing constraints, generate SDC, and develop timing ECOs.
- Identify convergence risks and collaborate with physical design, RTL, and DFT teams throughout project stages.
- Own timing closure and quality approval from pre-layout STA modeling through signoff.
- Use AI for timing optimization and data analysis.
Requirements
- Bachelor’s or master’s degree in Electrical Engineering.
- At least 5 years of hands-on static timing analysis experience.
- Experience with PrimeTime and signoff methodologies.
- Interest in using or learning AI tools.
Nice to have
- Experience with agentic frameworks, AI prompting, or Linux environments.
- TCL, Python, or shell scripting skills.
- Experience with data collection and analysis.