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Senior SoC Design Verification Engineer
Not specifiedFull-timeHardware EngineeringEnterprise SoftwareData Infrastructure
Join a research and development team building custom silicon for large-scale consumer and cloud computing products. Lead verification activities from planning through coverage closure and tape-out.
Responsibilities
- Plan verification for digital design blocks by understanding specifications and identifying key verification scenarios with design engineers.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry-standard formal tools.
- Define and implement coverage measures for corner cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Manage verification planning, test execution, coverage collection, and closure.
- Identify verification gaps and demonstrate progress toward tape-out.
Requirements
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- At least 8 years of experience creating and using verification components and environments with standard verification methodologies.
- Experience verifying digital logic at the RTL level for FPGAs or ASICs using SystemVerilog or Specman/E.
- Strong experience with digital design verification and verification environments.
Nice to have
- Master’s degree or PhD in Electrical Engineering or a related field.
- Experience with verification techniques and the full verification life cycle.
- Experience verifying ASIC performance and ASIC standard interfaces.
- Knowledge of memory system architecture.
- Experience across four or more SoC development cycles.