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Senior SoC Design Engineer

Google·Israel·
On-siteFull-timeHardware EngineeringEnterprise SoftwareData Infrastructure

Join a hardware engineering team developing custom silicon for large-scale cloud and consumer computing products. The role focuses on SoC and block-level RTL design, verification, optimization, and silicon bring-up. The position is based in Israel, with work locations available in Tel Aviv or Haifa;

Responsibilities

  • Define SoC and block-level design documentation, including interface protocols, block diagrams, transaction flows, and pipelines
  • Develop and debug RTL using Verilog and SystemVerilog
  • Debug functional and performance simulations and perform lint, formal verification, power format, and related checks
  • Participate in synthesis, timing and power closure, and ASIC silicon bring-up
  • Support block- and SoC-level test planning and coverage analysis
  • Collaborate with multidisciplinary, distributed engineering teams

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • At least 8 years of experience with digital design principles, RTL concepts, and Verilog or SystemVerilog
  • Experience optimizing RTL for synthesis, performance, and power
  • Experience with RTL design and debug alongside design verification

Nice to have

  • Python or Perl scripting experience
  • Experience with design sign-off and quality tools, including lint and clock-domain crossing checks
  • Knowledge of SoC architecture and assertion-based formal verification
  • Knowledge of PCIe, UCIe, DDR, AXI, or ARM processors

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Senior SoC Design Engineer – RTL and ASIC Development | CVZilla