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Senior RTL Design Engineer – SoC Clocking
On-siteFull-timeHardware EngineeringElectronics Manufacturing
Design and own system-on-chip clocking and reset logic for next-generation networking chips, from microarchitecture through verification, physical implementation, and tape-out.
Responsibilities
- Own SoC clock generation, distribution, muxing, division, switching, gating, and reset synchronization RTL
- Define and implement clock and reset architecture with the microarchitecture team
- Own clock-domain crossing infrastructure and CDC closure across the SoC
- Translate microarchitecture specifications into synthesizable Verilog/SystemVerilog RTL
- Partner with backend teams on clock-tree implementation, constraints, floorplanning, synthesis, timing, and congestion convergence
- Support software and firmware teams with clock programming, DVFS, and low-power flows
- Drive lint, CDC/RDC, formal, synthesis QoR, connectivity, and structural quality checks
- Support SoC integration, emulation, firmware, and post-silicon bring-up
- Develop automation for repeatable and scalable RTL integration and design-quality checks
Requirements
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering
- At least 3 years of relevant RTL or logic design experience
- Hands-on experience with Verilog and SystemVerilog RTL
- Understanding of synthesis, timing, and physical implementation impacts of RTL decisions
- Experience taking designs from microarchitecture specification through verification and physical implementation
- Knowledge of clock gating, clock muxing and dividers, glitchless switching, reset synchronization, and clock-domain crossing
- Familiarity with lint, CDC/RDC, formal, and synthesis tools
Nice to have
- Ownership of SoC-level clocking or reset architecture on a taped-out chip
- PLL or clock-generator integration experience
- Experience developing clock-tree constraints with backend teams
- Track record of clean deliveries to physical design, verification, emulation, firmware, and downstream teams