Senior RTL Design Engineer
Join a silicon design team developing large-scale devices for networking products. Design and integrate RTL, collaborate across verification and physical design, and support validation.
Responsibilities
- Write and review microarchitecture specifications.
- Implement Verilog/SystemVerilog RTL to meet timing, performance, and power requirements.
- Contribute to chip integration, timing methodology, and analysis.
- Collaborate with verification engineers to resolve bugs and achieve coverage closure.
- Work with physical design engineers to address timing and place-and-route issues.
- Support design methodology improvements and best practices.
- Debug issues, perform root-cause analysis, and support post-silicon lab validation.
Requirements
- BSc or MSc in Electrical Engineering
- At least 6 years of relevant experience
- RTL design experience
- Familiarity with UVM and functional verification methodologies
Nice to have
- Experience with MATLAB simulations and bit-exact modeling
- Familiarity with mixed-signal systems
- Knowledge and hands-on experience with clock domain crossing (CDC)