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Senior RTL Design Engineer
Not specifiedFull-timeHardware EngineeringCloud ComputingInternet Services
Join a hardware engineering team developing custom ASIC and SoC intellectual property for cloud and consumer products. The role covers microarchitecture, RTL development, verification support, quality checks, and silicon bring-up.
Responsibilities
- Define IP-level microarchitecture, including interface protocols, block diagrams, transaction flows, and pipelines.
- Develop and debug RTL using Verilog and SystemVerilog.
- Perform functional and performance simulation debugging and conduct Lint, CDC, formal verification, and UPF checks.
- Support synthesis, timing and power closure, and ASIC silicon bring-up.
- Contribute to verification test plans and block- and SoC-level coverage analysis.
- Collaborate with architecture, software, verification, power, timing, synthesis, and design-for-test teams.
- Evaluate design options for performance, power, and area.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- At least 4 years of experience with digital logic design, RTL concepts, and Verilog or SystemVerilog.
- Experience with logic design and debugging alongside design verification teams.
- Experience defining microarchitecture and technical specifications.
Nice to have
- Experience optimizing RTL for performance, power, and area through synthesis and low-power design techniques.
- Experience with design sign-off and quality tools such as Lint, CDC, and VCLP.
- Scripting experience with Python or Perl.
- Knowledge of SoC architecture, assertion-based formal verification, or high-performance and low-power design.
- Knowledge of PCIe, UCIe, DDR, AXI, or ARM processor architectures.