Senior Physical Design Engineer
Senior Physical Design Engineer responsible for complex physical design unit designs for high-speed communication chips. Involves place and route, verification, and optimization. Requires 5+ years experience and B.Sc. in Electrical Engineering, proficiency with EDA tools, and knowledge of advanced silicon processes.
Responsibilities
- Own complex physical design unit designs and ensure integration within innovative chip builds.
- Run, debug, and approve place and route (PnR) and verification flows across multiple projects.
- Perform physical design implementation, planning, and optimization for advanced chips.
Requirements
- B.Sc. or M.Sc. in Electrical Engineering.
- 5+ years of hands-on physical design place and route experience.
- Strong background in physical design methodology including synthesis, floorplan, clock tree synthesis, and routing.
- Experience with sign-off stages such as STA, PV, LEC, and EMIR.
- In-depth knowledge of advanced silicon process technologies.
- Familiarity with physical build EDA tools including Synopsys and Cadence.
- Collaborative team player.
Nice to have
- AI prompting experience.
- Experience in Linux environments.
- TCL, Python, shell scripting abilities.
- Experience with data collection and analysis.
- Understanding of chip and die verification process.