N
Senior GPU Architect, Deep Learning
On-siteFull-timeHardware EngineeringComputer Hardware
Define and drive future GPU architectures for deep learning and accelerated computing, from workload analysis and architectural modeling through design collaboration, validation, and silicon readiness.
Responsibilities
- Define and architect GPU hardware features for deep learning and parallel-processing workloads.
- Explore microarchitectural approaches across compute pipelines, memory hierarchy, data movement, synchronization, and performance efficiency.
- Analyze workloads and translate bottlenecks into architectural requirements and hardware proposals.
- Evaluate performance, power, area, complexity, and programmability tradeoffs.
- Develop and use functional and performance models to refine architecture before implementation.
- Collaborate with RTL, design, verification, compiler, and software teams through productization.
- Create architecture specifications, validation plans, and success criteria.
- Support work across workloads, models, RTL, and silicon as needed.
Requirements
- Bachelor’s, master’s, or doctoral degree in computer science, electrical engineering, computer engineering, or equivalent experience.
- At least 12 years of relevant industry experience in GPU architecture, computer architecture, or parallel processing architectures.
- Strong hardware architecture and microarchitecture background.
- Experience defining and evaluating architectural features, including performance, power, and area tradeoffs.
- Strong programming and scripting skills in C, C++, and Python.
- Experience with architectural modeling, simulation, or performance analysis.
- Background in parallel computing, memory systems, high-performance computing, or deep learning acceleration.
- Ability to communicate clearly and drive technical work across distributed, interdisciplinary teams.
Nice to have
- Deep knowledge of modern GPU architecture and hardware–AI workload interactions.
- Experience with memory subsystems, interconnects, coherence, scheduling, or execution pipelines.
- Experience with pre-silicon performance studies, workload characterization, and architectural correlation.
- Familiarity with training and inference behavior in large-scale deep learning models.
- Experience with silicon bring-up, debugging, or post-silicon analysis.