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Senior Design Verification Engineer – Peripheral IP

Qualcomm·Israel·
On-siteFull-timeHardware EngineeringSemiconductor Manufacturing

A semiconductor engineering team is seeking a Senior Design Verification Engineer to verify wired and wireless peripheral IP and subsystem designs for complex SoCs. The role is full-time and on-site five days per week in Haifa, with options to work from offices in Hod HaSharon or Ramat Gan.

Responsibilities

  • Verify peripheral IP and subsystem designs integrated into complex SoCs
  • Own end-to-end verification, including testbench architecture, planning, execution, and coverage closure
  • Develop and maintain UVM and SystemVerilog verification environments
  • Apply constrained-random testing, assertions, and coverage-driven methodologies
  • Debug complex issues in large-scale regression environments
  • Collaborate with design, architecture, software, and validation teams across sites
  • Provide technical guidance on verification methodology, debugging, and quality

Requirements

  • Bachelor’s or master’s degree in electrical engineering, computer engineering, science, or a related field
  • At least 5 years of hands-on design verification experience with SystemVerilog and UVM
  • Strong understanding of digital design fundamentals and IP- or SoC-level architectures
  • Proficiency in UVM testbench architecture, including agents, sequences, scoreboards, and coverage models
  • Experience with constrained-random and coverage-driven verification
  • Experience debugging complex issues in large regression environments
  • Scripting and automation skills using Python, Perl, Tcl, or shell in Linux/UNIX

Nice to have

  • Experience with USB, PCIe, Display, SerDes, or similar high-speed peripheral IP
  • Knowledge of low-power design, reset sequencing, and clock-domain interactions
  • Familiarity with regression management, verification metrics, and sign-off criteria
  • Experience working with global, cross-site teams
  • Interest in progressing toward technical or team leadership

Benefits

  • Opportunity to work on peripheral IP used in high-volume products
  • Technical environment with opportunities to lead, influence, and mentor
  • Collaboration with design, architecture, CAD, and validation teams
  • Growth path toward technical leadership or people management

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