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Physical Design STA Engineer
Not specifiedFull-timeHardware EngineeringSemiconductors
Develop physical design and signoff methodologies for networking chips and SoCs, working with block owners and full-chip STA engineers to support quality and timely convergence.
Responsibilities
- Develop physical design, static timing, logic-equivalence, and power-integrity flows and methodologies for networking chips and SoCs.
- Collaborate with block owners and full-chip STA engineers to support quality and timely convergence.
- Develop methodologies and tools for timing analysis and closure, power and noise analysis, IR-drop, electromigration, and backend verification across projects.
- Solve challenging physical design problems.
Requirements
- At least 2 years of relevant full-time experience.
- Strong knowledge of physical design, static timing analysis, and timing-closure methodologies.
- Familiarity with industry-standard tools such as PrimeTime and PrimePower.
- A bachelor's or master's degree in electrical engineering or computer engineering, or equivalent experience.
- Self-motivation, attention to detail, and strong written, verbal, and presentation skills.
- Ability to work independently and collaboratively with internal and global teams.
Nice to have
- Experience with signoff tools and domains including PrimeTime, PrimePower, RedHawk, Formality, and backend CAD.
- Knowledge of Tcl, Perl, or Python.