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Physical Design STA Engineer
On-siteFull-timeHardware EngineeringElectronics Manufacturing
An anonymized networking hardware team is seeking a Physical Design STA Engineer to perform static timing analysis and drive timing closure for high-speed communication devices.
Responsibilities
- Perform advanced static timing analysis at chiplet and full-chip levels
- Run PrimeTime and review and debug timing paths
- Understand timing constraints and generate SDC files
- Generate timing engineering change orders
- Identify convergence risks and collaborate with physical design, RTL, and DFT teams
- Own timing closure and quality approval from pre-layout STA modeling through signoff
Requirements
- B.Sc. in Electrical Engineering or Computer Engineering
- 2–3 years of experience as an STA Engineer
- Ability to adapt quickly to new technologies and investigate complex technical areas
- Strong communication and teamwork skills
- Demonstrated initiative in developing and implementing new solutions
Nice to have
- Knowledge of physical build flows and methodologies, including PNR, STA, and physical verification
- Familiarity with PrimeTime