Physical Design Engineer
Develop physical design, STA, and power integrity flows for cutting-edge networking chips. Collaborate with cross-functional teams on timing closure, power analysis, and methodology. B.Sc. in EE or equivalent, 2+ years experience, and proficiency in PrimeTime, Tcl/Python required.
Responsibilities
- Develop physical design, STA, and logic equivalence flows for networking chips and SoCs.
- Collaborate with block owners and full-chip STA engineers to ensure high-quality timing convergence.
- Create innovative solutions for physical design challenges in advanced chip design.
- Design and improve methodologies for timing analysis, power/noise analysis, IR-drop, EM, and back-end verification.
Requirements
- B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
- 2+ years of full-time relevant experience in physical design and STA.
- Proven knowledge in physical design, static timing analysis, and timing closure methodologies.
- Familiarity with industry tools such as PrimeTime (STA) and PrimePower (power estimation).
- Self-motivated with attention to detail and good communication skills.
- Ability to work independently and collaboratively in a global team.
Nice to have
- Experience in signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality).
- Knowledge in Tcl, Perl, or Python.
- Versatile and a great teammate.