Physical Design Engineer
Develop physical designs for networking silicon, optimizing power, performance, and area across the RTL-to-GDS flow.
Responsibilities
- Perform block-level physical design to meet specifications and power, area, and performance constraints.
- Resolve timing and congestion issues across high-cell-count and high-speed designs.
- Work across the RTL-to-GDS flow, including synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
- Contribute to design-flow development.
Requirements
- At least 2 years of relevant experience.
- Experience with RTL-to-GDS flows and methodologies.
- Knowledge of physical design flows, including place and route, static timing analysis, and physical verification.
- Understanding of physical design construction and integration.
- Knowledge of LVS/DRC verification methodologies.
- Familiarity with physical design EDA tools such as Synopsys or Cadence.
- Bachelor's or master's degree in electrical or computer engineering, or equivalent experience.