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Physical Design Engineer
Not specifiedFull-timeHardware EngineeringSemiconductors
Develop and improve physical design methodologies for networking chips and systems-on-chip, collaborating with design owners and project teams to deliver production-ready designs.
Responsibilities
- Develop physical design, synthesis, static timing analysis, and logic-equivalence methodologies for networking chips and systems-on-chip.
- Coordinate with block owners, chip-level timing engineers, and project managers to achieve quality and schedule goals.
- Develop and improve methodologies for floorplanning, power and clock distribution, place and route, timing closure, power and noise analysis, and back-end verification across projects.
- Solve physical design implementation challenges.
Requirements
- At least two years of relevant experience.
- Bachelor’s or master’s degree in electrical or computer engineering, or equivalent experience.
- Proficiency with Python, Perl, Tcl, and Make scripting.
- Expertise in analyzing and converging crosstalk delay, noise glitches, and electrical and manufacturing rules in deep-submicron processes.
- Knowledge of physical design optimization, including placement, routing, cell sizing, buffering, and logic restructuring, and implementing changes through ECOs.
- Knowledge of process-variation effects and design convergence that accounts for variation.
- Track record of delivering designs to production.
Nice to have
- Familiarity with Synopsys or Cadence synthesis, place-and-route, and static timing analysis tools.
- Experience defining methodologies or owning synthesis, place-and-route, or static timing analysis flows.