Performance Validation Engineer
Validate and debug DPU product performance and functional behavior across single-die and multi-die systems in simulation, emulation, and pre-silicon environments.
Responsibilities
- Analyze system-level operation of DPU products
- Debug and identify root causes of performance issues in RTL, waveform traces, and multi-die simulations
- Validate functional and performance behavior across current and future silicon devices
- Collaborate with design, verification, architecture, and performance modeling teams
- Develop validation methodologies for performance experiments and data collection
- Automate debug and validation activities to improve coverage and efficiency
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or an equivalent field
- At least 3 years of ASIC development or validation experience
- Strong ASIC debugging skills, including RTL reading, waveform analysis, and functional or performance root-cause analysis
- Hands-on experience with system-level performance validation and analysis
- Proficiency in Python and C/C++ in a Linux environment
- Ability to collaborate effectively with multidisciplinary engineering teams
Nice to have
- Experience with performance modeling, traffic generation, or architecture studies
- Knowledge of PCIe, Ethernet, CHI, or other modern interconnects and protocols
- Familiarity with Palladium, Veloce, FPGA prototyping, or similar emulation platforms