Logic Design Engineer
Join a leading silicon development team to design next-generation networking chips. You will write micro-architecture specifications, implement RTL in Verilog/SystemVerilog, collaborate on verification and physical design, and debug post-silicon. Requires B.Sc./M.Sc. in EE and 6+ years of relevant experience.
Responsibilities
- Write and review micro-architecture specifications based on architecture.
- Implement RTL designs using Verilog/SystemVerilog to meet timing, performance, and power targets.
- Contribute to full chip integration and timing methodology and analysis.
- Collaborate with verification engineers to resolve bugs and achieve coverage closure.
- Work with the physical design team to close timing and place-and-route issues.
- Perform debug, root-cause analysis, and post-silicon validation in the lab.
- Support design methodology evolution and best practices.
Requirements
- B.Sc./M.Sc. in Electrical Engineering from a top university.
- 6+ years of experience in a relevant field.
- RTL design experience.
- Familiarity with UVM and functional verification methodologies.
Nice to have
- Experience with MATLAB simulations and bit-exact modeling environments.
- Familiarity with mixed-signal systems and environments.
- Knowledge and hands-on experience with Clock Domain Crossing (CDC).