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Junior SoC Design Automation Engineer
Not specifiedFull-timeHardware EngineeringSemiconductors
Develop and support clock-related design flows and automation for SoC and networking chips, contributing to integration and design implementation across projects.
Responsibilities
- Develop and maintain SoC and networking clock design flows and methodologies.
- Improve SoC top-level automation scripts and flows using existing infrastructure and tools.
- Support SoC integration and construction flows across projects.
- Collaborate with design, STA, and project teams to support timely, high-quality design closure.
- Assist with timing, power, and noise analysis.
Requirements
- At least 2 years of experience in SoC design, design automation, or methodology development.
- BSc or MSc in Electrical or Computer Engineering, or relevant professional experience.
- Programming or scripting experience in at least one language.
- Understanding of physical design, including placement, routing, timing closure, and ECO implementation.
- Familiarity with EDA tools for synthesis, place-and-route, and timing analysis.
Nice to have
- Experience maintaining SoC design or automation flows.
- Knowledge of crosstalk, noise, and delay analysis.
- Experience with power or timing optimization.
- Python is preferred; Perl, Tcl, or Make are useful.
- Synopsys or Cadence EDA flow familiarity.