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Junior RTL Design Engineer
Not specifiedFull-timeHardware EngineeringCloud ComputingInternet Services
Develop custom ASIC and SoC intellectual property, from microarchitecture definition through RTL development and production. Work with architecture, software, verification, power, timing, and synthesis teams.
Responsibilities
- Define IP-level microarchitecture, including interface protocols, block diagrams, transaction flows, and pipelines
- Develop and debug RTL using Verilog and SystemVerilog
- Debug functional and performance simulations, and conduct Lint, CDC, formal verification, and UPF checks
- Contribute to synthesis, timing and power closure, and ASIC silicon bring-up
- Contribute to block- and SoC-level verification plans and coverage analysis
- Help improve design flows and automation, and define options for performance, power, and area
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- At least 4 years of experience with digital logic design, RTL concepts, and Verilog or SystemVerilog
- Experience with logic design and debug in collaboration with design verification teams
- Experience with microarchitecture and specifications
Nice to have
- RTL synthesis and optimization for performance, power, and area
- Low-power design techniques and design sign-off tools such as Lint, CDC, and VCLP
- Python or Perl scripting
- SoC architecture and assertion-based formal verification
- Knowledge of PCIe, UCIe, DDR, AXI, or ARM processors